View LTC2952IF_4622775.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

LTC2952 Push Button PowerPathTM Controller with Supervisor FEATURES

DESCRIPTION
The LTC(R)2952 is a power management device that features three main functions: push-button on/off control of system power, ideal diode power paths and system monitoring. The LTC2952's push-button input, which provides on/off control of system power, has independently adjustable ON and OFF debounce times. A simple microprocessor interface involving an interrupt signal allows for proper system housekeeping prior to power down. The ideal diode power paths provide automatic low loss switchover between two DC sources by regulating two external P-channel MOSFETs to have a small 20mV forward drop. High reliability systems may utilize the LTC2952's monitoring features to ensure system integrity. These features include: power-fail, voltage monitoring and P watchdog. The LTC2952 operates over a wide operating voltage range to accommodate a large variety of input power supplies. The part's combination of low 20mV external MOSFET regulation and very low standby current matches battery powered and power conscious application requirements.
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation. All other trademarks are the property of their respective owners.
Push-Button On/Off Control Automatic Low Loss Switchover Between DC Sources Wide Operating Voltage Range: 2.7V to 28V Low 25A Shutdown Current Guaranteed Threshold Accuracy: 1.5% of Monitored Voltage Over Temperature Adjustable Push-Button On/Off Timers Simple Interface Allows Graceful P Shutdown Extendable House Keeping Wait Time Prior to Shutdown 200ms Reset Delay and 1.6s Watchdog Time Out 8kV HBM ESD on PB Input 20 pin TSSOP and QFN (4mm x 4mm) Packages
APPLICATIONS

Desktop and Notebook Computers Portable Instrumentations Cell Phones, PDA and Handheld Computers Servers and Computer Peripherals Battery Backup Systems
TYPICAL APPLICATION
Push-Button Controller with Automatic Switchover Between Adapter and Battery
ADAPTER 3V TO 25V VIN Si6993DQ VOUT 1k 365k 511k G1 G2 V1 V2 VS PFI EN VM D1 M1 M2 PB ONT *22nF GND RST LTC2952 G1STAT PFO INT KILL WDE OFFT *68nF *OPTIONAL
2952 TA01
Ideal Diode vs Schottky Diode Forward Voltage Drop
1 CONSTANT RON CURRENT (A)
2.5V LT1767-2.5 SHDN Si6993DQ 100k D2 100k D3 1k 1k
10k
12V BATTERY
IDEAL DIODE CONSTANT VOLTAGE SCHOTTKY DIODE
0 P
0.02 FORWARD VOLTAGE (V)
0.50
2952 TA01b
2952f
1
LTC2952 ABSOLUTE MAXIMUM RATINGS
(Notes 1, 2)
Supply Voltages V1, V2, VS ............................................. -0.3V to 30V Input Voltages PB .................................... -6V to MAX (V1, V2, VS) V ONT, OFFT ................................................ -0.3V to 3V M1, M2, PFI, VM, WDE, KILL................... -0.3V to 7V Output Voltages G1, G2, EN .................... -0.3V to MAX (V1, V2, VS) V
G1STAT, PFO, RST, INT ............................ -0.3V to 7V Input Currents PB ...................................................... -1mA to 100A Operating Temperature Range LTC2952C ................................................ 0C to 70C LTC2952I ............................................. -40C to 85C Storage Temperature Range................... -65C to 150C Lead Temperature (Soldering, 10 sec) .................. 300C
PACKAGE/ORDER INFORMATION
TOP VIEW G1STAT TOP VIEW KILL M1 M2 M2 M1 KILL VM PFI WDE PB RST PFO 1 2 3 4 5 6 7 8 9 20 G1STAT 19 G1 18 V1 17 VS 16 V2 15 G2 14 EN 13 INT 12 GND 11 OFFT 6 PFO 7 ONT 8 OFFT 9 10 GND INT VM 1 PFI 2 WDE 3 PB 4 RST 5 21 15 V1 14 VS 13 V2 12 G2 11 EN G1
20 19 18 17 16
ONT 10
F PACKAGE 20-LEAD PLASTIC TSSOP TJMAX = 125C, JA = 90C/W
UF PACKAGE 20-LEAD (4mm x 4mm) PLASTIC QFN TJMAX = 125C, JA = 37C/W EXPOSED PAD (PIN 21), PCB GND CONNECTION OPTIONAL
ORDER PART NUMBER LTC2952CF LTC2952IF
F20 PART MARKING LTC2952CF LTC2952IF
ORDER PART NUMBER LTC2952CUF LTC2952IUF
UF20 PART MARKING 2952 2952
Order Options Tape and Reel: Add #TR Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF Lead Free Part Marking: http://www.linear.com/leadfree/ Consult LTC Marketing for parts specified with wider operating temperature ranges.
2952f
2
LTC2952 ELECTRICAL CHARACTERISTICS
SYMBOL VMAX IIN_OFF PARAMETER Operating Supply Voltage Quiescent Supply Current Both Ideal Diodes Switched Off (M1 = Open, M2 = 0V)
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V1 = V2 = VS = 2.7V to 28V unless otherwise noted. (Notes 2, 3)
CONDITIONS V1, V2 or VS V1 = 2.7V to 28V, V2 = 0V, VS = Open or V2 = 2.7V to 28V, V1 = 0V, VS = Open. Measured Current at V1 or V2. V1 = 2.7V to 28V, V2 = 3.5V, VS = Open. Measured Current at V1. V1 = 2.7V to 28V, V2 = 3.5V, VS = Open. Measured Current at V2.

MIN 2.7
TYP 24
MAX 28 60
UNITS V A

5 23 65
15 50 170
A A A
IIN_ON
Quiescent Supply Current Both Ideal Diodes Switched On (M1 = 0V, M2 = 0V) V2 Preferential Threshold Voltage (M1 = Open, M2 = 0V) (Note 4) V1, V2 and VS Inter Pin Leakage to the Highest Supply Ideal Diode Power Path Forward Regulation Voltage Ideal Diode Power Path Fast Reverse Turn-Off Threshold Voltage Gate Turn-Off Current Gate Turn-On Current
V1 = VS = 2.7V to 28V, V2 = 0V or V2 = VS = 2.7V to 28V, V1 = 0V. Measured Combined Current at V1 and VS or V2 and VS. V1 = 28V, VS = Open. V1 = 28V, V2 = VS = 0V; V1 = VS = 0V, V2 = 28V; V1 = V2 = 0V, VS = 28V (V1 or V2) - VS, 2.7V (V1 or V2) 28V (V1 or V2) - VS, 2.7V (V1 or V2) 28V IG -100A/mV G1 = G2 = VMAX - 1.5V V1 = V2 = 2.7V to 28V, VS = (V1 or V2) - 40mV, G1 = G2 = VMAX -1.5V. V1 = V2 = 2.7V to 28V, VS = (V1 or V2) + 0.1V, G1 = G2 = VMAX -1.5V. V1 = V2 = 5V to 28V, VS = (V1 or V2) - 0.1V, G1 = G2 = VMAX - 1.5V. IGX = 2A, VX = 8V to 28V, VS = VX - 0.1V Measure VX - VGX IGX = -2A, VX = 2.7V to 28V, VS = VX + 0.1V Measure VMAX - VGX VG(OFF) to VGS -3V, CGATE = 1nF (Note 5), V1 = V2 = 12V VG(ON) to VGS -1.5V, CGATE = 1nF (Note 6), V1 = V2 = 12V IPB = -1A VPB(VOC) < VPB 28V 0V VPB < VPB(VOC) PB Falling From High to Low
V2PREF_TH ILEAK
3.3
3.8 3
V A
Ideal Diode Function VFR VRTO IG(SRC) IG(SNK)

10 -20 -2 2
20 -35 -5 5
35 -64 -10 10
mV mV A A
IG(FASTSRC)
Gate Fast Turn-Off Source Current
-0.5
-2.5
-10
mA
IG(FASTSNK)
Gate Fast Turn-On Sink Current
0.3
0.7
2
mA
VG(ON) VG(OFF) tG(ON) tG(OFF)
Gate Clamp Voltage Gate Off Voltage Gate Turn-On Time Gate Turn-Off Time

6
7 0.2
8 0.4 10 10
V V s s
0.1 0.1
2.5 2.5
Push-Button Pin (PB) PB Open Circuit Voltage VPB(VOC) PB Input Current IPB VTH_PB VHYS_PB PB Input Threshold Voltage PB Input Hysteresis

1 -1 0.65 10
4 -10 0.77 25
6 1 -25 0.8 150
V A A V mV
2952f
3
LTC2952 ELECTRICAL CHARACTERISTICS
SYMBOL IONT,OFFT tDB,ON/OFF PARAMETER Debounce Time Pins (ONT, OFFT) ONT/OFFT Pull-Up/Pull-Down Current VONT, VOFFT = 0V (Pull-Up), VONT, VOFFT = 1.5V When Timer is Active (Pull-Down) Internal Default On-Time/Off-Time tDB,ON: CONT = Open, Measured Time Between PB Low EN High, tDB,OFF: Measured Time Between PB Low INT High

The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V1 = V2 = VS = 2.7V TO 28V unless otherwise noted. (Notes 2, 3)
CONDITIONS MIN 1.6 18 TYP 2.0 26 MAX 2.4 34 UNITS A ms
tONT,OFFT
Additional Adjustable Turn-On/TurnCONT = 1500pF, COFFT = 1500pF Off Time (Note 7) Accurate Comparator Input Pins (VM, PFI, M1, M2, KILL) VTH_VM VTH VHYS IIN_LKG IM1_SRC VM1(VOC) IM1_LKG VWDE(H,TH) VWDE(L,TH) IWDE(IN,HL) IWDE(IN,HZ) IOUT_LKG VOL IEN(LKG) VEN(VOL) VM Input Reset Threshold PFI, M1, M2, KILL Input Threshold Voltage PFI, M1, M2, KILL Input Hysteresis VM, PFI, M2, KILL Input Current M1 Input Pull-Up Current M1 Voltage Open Circuit M1 Input Leak Current Input High Threshold Voltage Input Low Threshold Voltage High Low Input Current (Note 8) VWDE = 0.7V, 1.1V VPIN = 5V IPIN = 1mA VEN = 28V, EN Sink Current Off IEN = 3mA V1 = 1.2V and/or V2 = 1.2V, IEN = 100A Voltage Monitor/Watchdog Timing tRST tWDE tWDE(PW MIN) tVM(UV) tPFI Reset Time-Out Period Watch-Dog Time-Out Period Minimum Period Between Consecutive Edges VM Undervoltage Detect to RST PFI Delay to PFO VM Less Than VTH_VM by more than 1% PFI More or Less Than VPFI_TH by more than 1% M1 = 6V Both Falling and Rising Falling
10
15
20
ms

0.492 0.492 5 -1.5 1
0.500 0.500 15 -3 4
0.508 0.508 25 0.1 -5 6 0.1 1.5
V V mV A A V A V V A A
V = 0.5V M1 = 1V

Watch-Dog/Extend Pin (WDE) 0.3 25 10 1 0.4 1 0.4 0.05 140 1.1 200 1.6 5 150 150 0.3 260 2.1 10
High Z Input Current Open Drain Output Pins (G1STAT, INT, RST, PFO) Leakage Current Voltage Output Low EN Leakage Current EN Voltage Output Low
A V A V V ms s s s s
High Voltage Open Drain Output Pin (EN)
2952f
4
LTC2952 ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER P Handshake Timing INT Minimum Pulse Width tINT(MIN) tKILL(PW) tKILL,ON BLANK tKILL, OFF WAIT tEN, LOCKOUT KILL Minimum Pulse Width KILL ON Blanking (Note 9) KILL Wait Time (Note 10) Enable Lockout Time (Note 11)
The denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25C. V1 = V2 = VS = 2.7V to 28V unless otherwise noted. (Notes 2, 3)
CONDITIONS Minimum Measured Time PB Rising to INT Rising Full Swing Pulse From 5V to 0V KILL = 0V, Measured Time Between EN Rising EN Falling KILL = 1V, COFFT = OPEN, Measured Time Between INT Falling EN Falling Measured Time Between EN Falling EN Rising

MIN 10
TYP 50 150
MAX 250 500 530 530 530
UNITS s s ms ms ms
270 270 270
400 400 400
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime. Note 2: The greatest of V1, V2 or VS is the internal supply voltage (VMAX). Note 3: All currents into pins are positive; all voltages are referenced to GND unless otherwise noted. Note 4: V2PREF_TH is the minimum voltage level at which V2 becomes the preferential source of quiescent current when both of the ideal diodes are off. Note 5: VS is stepped from (V1 or V2) + 0.2V to (V1 or V2) - 0.2V to trigger the event. The gate voltages are initially VG(OFF). Note 6: VS is stepped from VX - 0.2V to VX + 0.2V to trigger the event. Gate voltages are initially clamped at VG(ON). Note 7: The Adjustable Turn-On and Turn-Off timer period is the adjustable debounce period following the Internal Default-On and Default-Off timer period respectively.
Note 8: The input current to the three-state WDE pin are the pull-up and the pull-down current when the pin is either set to 3.3V or GND respectively. In the Open state, the maximum pull-up or pull-down leakage current permissible is 10A. Note 9: The Turn-On KILL Blanking Time is the waiting period immediately following the EN pin switching high; at the end of this period the input to the KILL needs to be high to indicate that the system has powered up properly, otherwise the EN pin is immediately switched low. Note 10: The KILL Wait Time during the power down process is the wait period immediately following a valid turn-off command until the EN pin switches low. Note 11: The Enable Lockout Time is the minimum wait time between the last falling edge and the next rising edge on the EN pin.
2952f
5
LTC2952 TI I G DIAGRA S
Ideal Diode Function - Gate Turn-On and Turn-Off Time
12.2V VS 12V 12.05V VGX VX = 12V tG(ON) 9V 5.3V tG(OFF) 10.5V
2952 TD01
Push-Button Debounce Times, KILL Wait Time and Enable Lockout Time with KILL Above Threshold
PB EN INT tDB,ON tONT 0.775V 0.5*VPULL-UP 0.5*VPULL-UP t < tOFFT tDB,OFF tOFFT tDB,OFF tINT(MIN) tKILL, OFF WAIT t > tONT tDB,ON tEN, LOCKOUT
2952 TD02
6
W
UW
12.2V 11.8V 12V 12.05V
KILL ON Blanking with KILL Below Threshold
KILL EN 0.5*VPULL-UP tKILL, ON BLANK 0.5*VPULL-UP
2952 TD03
2952f
LTC2952 TI I G DIAGRA S
PFI and PFO
PFI 0.515V 0.5*VPULL-UP tPFI tPFI 0.500V 0.5*VPULL-UP
2952 TD04
VM WDE DON'T CARE DON'T CARE DON'T CARE DON'T CARE
RST tRST 200ms tWDE 1.6s tRST 200ms W
UW
PFO
WDE Minimum Pulse Width
WDE tWDE(PW MIN)
2952 TD05
VM, WDE and RST
tVM(UV)
2952 TD06
2952f
7
LTC2952 TYPICAL PERFORMANCE CHARACTERISTICS
Specifications are at TA = 25C unless otherwise noted. IIN-OFF vs Input Supply Voltage at Different Temperatures
50 130C 100 40 IIN_OFF (A) 90C 90 IIN_ON (A) 25C 30 -45C -60C 20 V1 = VIN, V2 = 0, VS = OPEN OR V2 = VIN, V1 = 0,VS = OPEN M1 = OPEN, M2 = 0V 10 0 15 5 10 20 25 INPUT SUPPLY VOLTAGE VIN (V) 30
2952 G01
IIN-ON vs Input Supply Voltage at Different Temperatures
110 V1 = VS = VIN, V2 = 0V OR V2 = VS = VIN, V1 = 0V 130C 90C V2 PREF_TH (V) 25C 3.4 3.5
V2 Preferential Threshold vs Temperature
V1 = 28V, VS = OPEN
80 70 60 50 40 0 15 5 10 20 25 INPUT SUPPLY VOLTAGE VIN (V)
3.3
-45C -60C
3.2
3.1
30
2952 G02
3.0 -50
-25
50 0 25 75 TEMPERATURE (C)
100
125
2952 G03
Worst Case Supply to Supply Leakage vs Temperature
1000 V2 = VS = 0V, V1 = 28V V1 = VS = 0V, V2 = 28V V1 = V2 = 0V, VS = 28V 100 ILEAK (nA) IPB (A) 20 0 -20 - 40 -60 -80 -100 1 -50
PB Current vs PB Voltage
2.4 V1 = V2 = VS = 28V
ONT/OFFT Pull-Up/Pull-Down Current vs Temperature
2.2 IONT, OFFT (A)
2.0
10
1.8
-25
0 25 50 75 TEMPERATURE (C)
100
125
2952 G04
-120 -10 -5
0
5 10 15 20 PB VOLTAGE (V)
25
30
1.6 -50
-25
50 25 75 0 TEMPERATURE (C)
100
125
2952 G06
2952 G08
Total Turn-On/Turn-Off Time vs ONT/OFFT Capacitors Value
10000 0.508 0.506 tDB, ON/OFF + tONT, OFFT (ms) 0.504 1000 VTH (V)
KILL, PFI, M1 and M2 Falling Input Threshold Voltage vs Temperature
0.508 0.506 0.504 VTH_VM (V) 0.502 0.500 0.498 0.496 0.494 -25 50 25 75 0 TEMPERATURE (C) 100 125
VM Input Reset Threshold Voltage vs Temperature
0.502 0.500 0.498
100 0.496 0.494 10 0.1 0.492 -50
1
10 100 CONT/COFFT (nF)
1000
2952 G10
0.492 -50
-25
50 25 75 0 TEMPERATURE (C)
100
125
2952 G11
2952 G13
2952f
8
LTC2952 TYPICAL PERFORMANCE CHARACTERISTICS
Specifications are at TA = 25C unless otherwise noted. KILL ON Blanking, KILL Wait Time, Typical Transient Duration vs Enable Lockout Time vs Temperature Comparator Overdrive at Different Input Voltages (VM, KILL, PFI, M1 and M2)
tKILL, ON BLANK/tKILL, OFFWAIT/tEN, LOCKOUT (ms) 10 TYPICAL TRANSIENT DURATION (ms) 480 260 240 440 V1 = V2 = VS = 28V 220 tRST (ms) 400 V1 = V2 = VS = 2.7V 360 160 320 -50 140 -50 200 V1 = V2 = VS = 2.7V 180 V1 = V2 = VS = 28V
Reset Time-Out Period vs Temperature at Different Input Voltages
1 COMPARATOR TRIPS ABOVE CURVE
0.1
0.01 0.01
0.1
1
10
100
2952 G14
-25
COMPARATOR OVERDRIVE VOLTAGE (% OF VTH)
50 25 75 0 TEMPERATURE (C)
100
125
-25
25 50 75 0 TEMPERATURE (C)
100
125
2952 G16
2952 G17
Watch Dog Time Period vs Temperature at Different Input Voltages
2.0 5.0
G1STAT, PFO, INT and RST PullDown Current vs Supply Voltage
V1 = V2 = VS = VMAX PULLDOWN CURRENT (mA) 4.0 PIN AT 150mV 2.5
G1STAT, PFO, INT and RST Voltage Output Low vs Pull-Down Current at Different Temperatures
V1 = V2 = VS = 12V 2.0 130C 90C
1.8 V1 = V2 = VS = 28V tWDE (s) 1.6 V1 = V2 = VS = 2.7V 1.4
VOL (V)
3.0
1.5
25C -45C
2.0 PIN AT 50mV 1.0
1.0
-60C
0.5
1.2 -50
0 -25 50 25 75 0 TEMPERATURE (C) 100 125 0 5 20 15 25 10 SUPPLY VOLTAGE - VMAX (V) 30
2952 G19
0 0 5 20 15 25 10 PULL DOWN CURRENT (mA) 30
2952 G20
2952 G18
EN Pull-Down Current vs Supply Voltage
10 V1 = V2 = VS = VMAX EN AT 150mV PULLDOWN CURRENT (mA) PULLDOWN CURRENT (A) 8 1000 100 10 1 0.1 10000
EN Pull-Down Current vs Supply Voltage
2.5 V1 = V2 = VS = VMAX EN AT 150mV 2.0 EN AT 50mV VEN (VOL) (V) 1.5
EN Voltage Output Low vs Pull-Down Current at Different Temperatures
V1 = V2 = VS = 12V 130C 90C
6
25C 1.0 -45C -60C 0.5
4 EN AT 50mV 2
0.01 0 0 5 20 15 25 10 SUPPLY VOLTAGE - VMAX (V) 30
2952 G21
0.001 0 0.2 1 1.2 1.4 0.4 0.6 0.8 SUPPLY VOLTAGE - VMAX (V) 1.6
0 0 10 40 50 30 60 20 PULL DOWN CURRENT (mA) 70
2952 G23
2952 G22
2952f
9
LTC2952 PIN FUNCTIONS
(TSSOP/QFN)
EN (Pin 14/Pin 11): DC/DC Enable Output. This pin is a high voltage open drain pull-down used to control system power. EN pin goes high impedance after an initial turn-on command (via either the digital on or a valid push-button on - refer to the Applications Information section). EN pin pulls low at the end of a valid power-down sequence, or when KILL pin is driven low anytime after a valid powerup sequence. Exposed Pad (Pin 21, QFN Package): The Exposed Pad may be left open or connected to device ground. G1 (Pin 19/Pin16): Primary P-Channel MOSFET Gate Drive Output. When the primary ideal diode function is enabled and in regulation, the ideal diode controller drives this pin to maintain a forward voltage (VFR) of 20mV between the V1 and VS pins. When another power source is driving the VS pin, causing the voltage level at the VS pin to be greater than the voltage level at the V1 pin or when the primary ideal diode driver is disabled via the mode select input pins, this pin pulls up to the MAX(V1, VS) voltage, turning off the primary P-channel power switch. Leave this pin open when primary ideal diode function is not used. G1STAT (Pin 20/Pin 17): Open-Drain Primary Ideal Diode Status Output. When the primary P-channel power switch is off, the G1STAT pin will go from an open state to a strong pull-down. This pin can be used to signal the state of the primary ideal diode power path to a microcontroller. Leave this pin open or tied to GND when unused. G2 (Pin 15/Pin 12): Secondary P-Channel MOSFET Gate Drive Output. When the secondary ideal diode function is enabled and in regulation, the ideal diode controller drives this pin to maintain a forward voltage (VFR) of 20mV between the V2 and VS pins. When another power source is driving the VS pin, causing the voltage level at the VS pin to be greater than the voltage level at the V2 pin or when the secondary ideal diode driver is disabled via the mode select input pins, this pin pulls up to the MAX(V2, VS) voltage, turning off the secondary P-channel power switch. Leave this pin open when secondary ideal diode function is not used.
GND (Pin 12/Pin 9): Device Ground. INT (Pin 13/Pin 10): Interrupt Output. This pin is an open drain pull-down pin used to signal the system that a power shutdown is imminent. The INT pin asserts low 26ms after the intial falling edge of the push button off event and during the power down sequence. Leave this pin open or tied to GND if interrupt signal is unused. KILL (Pin 3/Pin 20): System Power Shutdown Input. Set ting this pin low asserts the EN pin low. In modes where M1 is above threshold, setting this pin low also shuts off the ideal diodes. During system turn-on, input to this pin is ignored until 500ms (tKILL,ON BLANK) after the EN pin first becomes high impedance. This pin has an accurate 0.5V falling threshold and can be used as a voltage monitor input. M1 (Pin 2/Pin 19): Mode Select Input 1. Input to an accurate comparator with 0.5V falling threshold and 15mV hysteresis. Has a 3A internal pull-up to an internal supply (4V). Together with M2 determines the ideal power path and on/off control behavior of the part. Refer to the Operation and Applications Information sections for configurations based on the voltage levels at M1 and M2. M2 (Pin 1/Pin 18): Mode Select Input 2. High impedance input to an accurate comparator with 0.5V falling threshold and 15mV hysteresis. When M1 is low, M2 controls whether the primary (G1) ideal diode function is enabled. When M1 is high, M2 acts as a digital on/off control input: A rising edge on this pin is interpreted as a turn-on command and a falling edge is interpreted as a turn-off command. Refer to the Operation and Applications Information sections for configurations based on the voltage levels at M1 and M2. OFFT (Pin 11/Pin 8): Off Timing Input. Attach 110pF of external capacitance (C OFFT ) to GND for each additional millisecond of turn-off debounce time beyond the internally set 26ms. Leave open if additional debounce time is not needed.
2952f
10
LTC2952 PIN FUNCTIONS
(TSSOP/QFN)
ONT (Pin 10/Pin 7): On Timing Input. Attach 110pF of external capacitance (CONT) to GND for each additional millisecond of turn-on debounce time beyond the internally set 26ms. Leave open if additional debounce time is not needed. PB (Pin 7/Pin 4): Push-Button Input. Input to a comparator with 0.775V falling threshold and 25mV hysteresis. PB has a 10A internal pull-up to an internal supply (4V). This pin provides on/off power supply control via the EN pin, which is typically connected to an external DC/DC converter. Setting the PB pin low for a time determined by the ONT timing capacitor toggles the EN pin high impedance. Letting this pin toggle high and then setting this pin low again for 26ms asserts INT low. After the INT pin asserts low, if the PB pin is still held low for a time determined by the OFFT timing capacitor, the process of turning off the system power begins. At the end of the turn-off process, the EN pin is set low. Leave this pin open if push button function is not used. PFI (Pin 5/Pin 2): Power Fail Input. High impedance input to an accurate comparator with a 0.5V falling threshold and 15mV hysteresis. This pin controls the state of the PFO output pin. Tie to device GND if power fail monitoring function is not used. PFO (Pin 9/Pin 6): Power Fail Output. This pin is an open drain pull-down which pulls low when the PFI input is below 0.5V. Leave this pin open or tied to GND if power fail monitoring function is not used. RST (Pin 8/Pin 5): Reset Output. This pin is an open drain pull-down. Pulls low when VM input is below 0.5V and held low for 200ms after VM input is above 0.5V. Also pulls low for 200ms when the watchdog timer (1.6s) is allowed to time out. Leave this pin open or tied to GND if voltage monitoring function is not used. V1 (Pin 18/Pin 15): Primary Input Supply Voltage: 2.7V to 28V. Supplies power to the internal circuitry and is the anode input of the primary ideal diode driver (the cathode input to the ideal diode drivers is the VS pin). A battery or other primary power source usually provides power to this input. Minimize the capacitance on this pin in applications
where the pin can be high impedance (disconnected or inherent high source impedance). Otherwise, an optional bypass capacitor to ground in the range of 0.1F to 10F can be used. V2 (Pin 16/Pin 13): Secondary Input Supply Voltage: 2.7V to 28V. Supplies power to the internal circuitry and is the anode input of the secondary ideal diode driver (the cathode input to the ideal diode drivers is the VS pin). A secondary power source such as a wall adapter, usually provides power to this input. Minimize the capacitance on this pin in applications where the pin can be high impedance (disconnected or inherent high source impedance). Otherwise, an optional bypass capacitor to ground in the range of 0.1F to 10F can be used. VM (Pin 4/Pin 1): Voltage Monitor Input. High impedance input to an accurate comparator with a 0.5V threshold. Together with the WDE pin controls the state of the RST output pin. Tie to device GND if voltage monitoring function is not used. VS (Pin 17/Pin 14): Power Sense Input. This pin supplies power to the internal circuitry and is the cathode input to the ideal diode drivers (the anode inputs to the ideal diode drivers are the V1 and V2 pins). Bypass this pin to ground with one or more capacitors of at least 0.1F. WDE (Pin 6/Pin 3): Watchdog/Extend Input. A three-state input pin. A rising or falling edge must occur on this pin within a 1.6s watch-dog timeout period (while the RST output is high impedance), to prevent the RST pin from going low. The watchdog function of this pin is disabled when both of the ideal diode drivers are disabled in certain power path configurations (refer to the Application Information section). During a shutdown process: a rising or falling edge on this WDE pin within the 500ms tKILL,OFF WAIT period extends the waiting period another 500ms before the EN line is set low. This extend process can be repeated indefinitely in order to provide as much time as possible for the microprocessor to do its housekeeping functions before a power shut-down. Leave open or drive in high-Z state with a three-state buffer to disable watchdog or extend function or both.
2952f
11
LTC2952 BLOCK DIAGRAM
SECONDARY SUPPLY TO LOAD PRIMARY SUPPLY
V2
VS
V1
IDEAL DIODE DRIVER 2
VIN
VS
V2
VS
V1
VS
VIN
IDEAL DIODE DRIVER 1
-
A2
+
-
A1
+
GATE G2
LINEAR GATE DRIVER AND VOLTAGE CLAMP
ANALOG CONTROLLER
LDO/BAND GAP REF VCC 0.5V 0.775V
ANALOG CONTROLLER
LINEAR GATE GATE DRIVER AND VOLTAGE CLAMP STAT ON/OFF
G1 G1STAT
INTERNAL ENABLE
INTERNAL ENABLE
KILL 0.5V
VCC 10A
LOGIC CP6 200S FILTER
PB 0.775V
PUSH-BUTTON OSCILLATOR ONT
OFFT
WDE 0.5V CP1
200ms RST DELAY/ 1.6s WATCHDOG TIMER
VM PFO RST
12
+
THREE-STATE/ EDGE DETECTOR
CP2
-
-
PUSH-BUTTON DETECT
CP3
-
VCC M2 3A
CP4
CP5
+ +
+ + -
- - +
0.5V
M1 0.5V
GND
EN
INT
MONITORS 0.5V
PFI
2952 BD
2952f
LTC2952 OPERATION
The LTC2952 is designed to simplify applications requiring management of multiple power sources. The three main features of the part are: push-button control, ideal diode power paths and system monitoring. The block diagram on the previous page shows the part divided into its main functional blocks. The push-button detect block is responsible for debouncing any push-button event on the PB pin. Note that the ON and OFF debounce times can be configured independently by using two separate capacitors on the ONT and OFFT pins respectively. A valid push-button on event will set the EN pin high impedance and a valid off event will drive the EN pin low. In a typical application the EN pin is tied to the shutdown pin of a DC/DC converter. Therefore by toggling the EN pin, the push-button pin has a direct control over the enabling/ disabling of an external DC/DC converter. This control of system turn-on/off is done in a graceful manner which ensures proper system power up and power down. The ideal diode drivers regulate two external P-channel MOSFETs to achieve low loss switchover between two DC sources. Each driver regulates the gate of the PFET such that the voltage drop across its source and drain is 20mV. When the load current is larger than the PFET ability to deliver such current with a 20mV drop across its source and drain, the voltage at the gate clamps at VG(ON) and the PFET behaves like a fixed value resistor. Besides providing ideal-diode power paths and control of system power turn-on/off, the LTC2952 also provides system monitoring function via the VM, WDE, RST and PFI, PFO pins. The voltage monitoring (VM) and the watchdog (WDE) input pins determine the state of the RST output with 200ms reset time and 1.6s watchdog time. The PFI and PFO pins are the input and output of an accurate comparator that can be used as an early power fail monitor. The KILL, M1 and M2 pins are the inputs to accurate comparators with 0.5V threshold. The outputs of these comparators interact with the logic block to alter the idealdiode power paths and the push-button control behavior. Specifically, the KILL input provides the system with a capability to turn off system power at any point during operation. The M1 and M2 pins are mode pins that configure the part to have different behaviors in the power path switchover of the two DC sources. Figure 1 shows the four different typical configurations of the LTC2952. In Configuration A, both of the idealdiode power paths are always enabled which results in an automatic switchover between the two DC sources. Configuration C is similar to A except for the push-button input which now controls both the EN pin and the ideal diode power paths. In Configurations B and D, M2 is used as a voltage monitor. In B, when the M2 input is above its threshold the primary ideal diode power path is disabled. In D, M2 needs to be above threshold before PB has control over the EN pin and the ideal diode power paths. Furthermore in D, the rising and falling edges on M2 are interpreted as turn-on and turn-off commands respectively.
2952f
13
LTC2952 OPERATIO U
DC2 IDEAL DIODE 2 DC1 DC/DC SHDN DC2 IDEAL DIODE 2 DC1 IDEAL DIODE 1 V2 V1 G1 IDEAL DIODE DRIVER 1 DC/DC SHDN IDEAL DIODE 1 V2 V1
-
M2
+ + -
PB DETECT LOGIC PB EN PB 0.5V PB DETECT LOGIC EN
CONFIGURATION A M1 = 0, M2 = 0
CONFIGURATION B M1 = 0
DC2 IDEAL DIODE 2 DC1 IDEAL DIODE 1 V2 V1 G1 AND G2 DC/DC SHDN
DC2 IDEAL DIODE 2 DC1 IDEAL DIODE 1 V2 V1 G1 AND G2 IDEAL DIODE DRIVER 1 AND 2 DC/DC SHDN
-
IDEAL DIODE DRIVER 1 AND 2 M2
+ + -
PB DETECT LOGIC PB EN PB 0.5V PB DETECT LOGIC EN
CONFIGURATION C M1 = 1, M2 = 1
CONFIGURATION D M1 = 1
2952 F01
Figure 1. Four Different Typical Power Path Configurations
2952f
14
LTC2952 APPLICATIONS INFORMATION
The LTC2952 is a versatile power management IC with pushbutton on/off control and system supervisory features. The power management function features ideal diode power path control that provides low loss switchover between two DC sources. This power path control behavior is configurable to satisfy various application requirements. The LTC2952's push-button input has independently adjustable ON and OFF debounce times that control the toggling of a low-leakage open drain enable output and in some configurations, the ideal diode power path operation. A simple interface allows for digital on/off control and proper system housekeeping prior to power down. The LTC2952 also features robust and accurate system supervisory functions that fit high reliability system applications. These supervisory functions include power-fail, voltage monitoring and watchdog reset functions which can be used to monitor power status and ensure system integrity. The Ideal Diode Drivers In a typical application, each of the ideal diode drivers is connected to drive an external P-channel MOSFET as shown in the Block Diagram and Figure 2. When power is available at VIN and the ideal diode driver is enabled, the ideal diode driver regulates the voltage at the GATE to maintain a 20mV difference between VIN and VS. As the load current varies, the GATE voltage is controlled to maintain the 20mV difference. If the load current exceeds the external PFET's ability to deliver the current with a 20mV VDS, then the voltage at the GATE clamps and the PFET behaves as a fixed resistor causing the forward voltage to increase slightly as the load current increases. When the VS pin is externally pulled up above the voltage level at VIN, the ideal diode driver shuts the external PFET off to prevent reverse conduction. Thus when both the primary and secondary ideal diode drivers are enabled, the two ideal diode drivers work together to bring VS to within 20mV of the higher of either V1 or V2. The G1STAT pin indicates the status of the primary ideal diode driver. If the external PFET connected to the primary driver is providing power to VS, the G1STAT pin is in a high impedance state and when the PFET connected to the primary driver is shut-off, the G1STAT pin pulls low. POWER PATH CONFIGURATIONS Configuration A: Push-Button Controller with Automatic Switchover Between WALL Adapter and Battery In this particular configuration both of the M1 and M2 pins are connected to ground. These connections set up the LTC2952 to operate with both of the ideal diodes enabled all the time. In this application, power from the VS node to the system is controlled through the EN pin connected to a shutdown
* ADAPTER Q2
+ INPUT SUPPLY - VIN V1/V2 VS VS
+ - OUTPUT TO LOAD
BATTERY
Q1 G1 VS
TO SYSTEM DC/DC SHDN
ANALOG CONTROLLER
INTERNAL ENABLE
Figure 2. Detailed Ideal Diode Driver Functional Block Diagram
+
A1
-
PRIMARY/SECONDARY IDEAL DIODE DRIVER G2 V1 V2 LINEAR GATE DRIVER AND VOLTAGE CLAMP M1 G1/G2 GATE G1STAT STAT (ONLY IN PRIMARY DRIVER)
2952 F02
LTC2952
EN *Q1 AND/OR Q2 PFET CAN BE REPLACED BY A SCHOTTKY DIODE WITH G1 AND/OR G2 FLOATING
M2 PB
ON/OFF
S1
2952 F03
Figure 3. Power Path Configuration A
2952f
15
LTC2952 APPLICATIONS INFORMATION
pin of a DC/DC converter. The PB input achieves power path control by toggling this EN pin. Note that in this application both of the ideal diodes are enabled all the time, therefore either Q1 or Q2 can be replaced by Schottky diodes as long as the voltage drop across the Schottky diodes and their reverse leakage currents are acceptable. Configuration B: Push-Button Controller with Preferential WALL Adapter Operation and Automatic Switchover to Battery In this configuration (Figure 4) the M1 pin is connected to ground and the M2 pin is used as a monitor on the Wall Adapter input to alter the behavior of the ideal diode drivers. When the Wall Adapter Voltage is below the trip threshold, both of the ideal diodes are enabled. When the Wall Adapter Voltage is above the trip threshold, the primary ideal diode driver is disabled (shutting off Q1 and Q3) and the secondary ideal diode driver is enabled (turning on Q2). This means the load current will be supplied from the Wall Adapter (V2) regardless of the voltage level at the battery (V1). If the wall Adapter Voltage trip threshold is set lower than the Battery input voltage level and the Wall Adapter input can go high impedance, the capacitance on V2 needs to be minimized. This is to ensure proper operation when the Wall Adapter goes high impedance and Q1, Q3 is instantly turned on.
S1 WALL ADAPTER
2952 F05
Noting the possible current path through the PFET body diode, a back-to-back PFET configuration must be used for Q1, Q3 to make sure that no current will flow from the battery (V1) to the VS pin even if the Wall Adapter (V2) Voltage is less than the battery (V1) Voltage. Configuration C: Push-Button Control of Ideal Diode Drivers In this configuration the M2 pin is tied to the M1 pin. Since the M1 pin has a 3A internal pull-up current, this current causes both M1 and M2 to pull high. This allows the PB pin to have complete control of both the ideal diode drivers and the EN pin. The first valid push-button input turns on both of the ideal diode drivers causing the VS pin to be driven to the higher of either the Wall Adapter or the Battery input - providing power to the system directly. Conversely, a valid push-button off input turns off the ideal diodes after the shutdown sequence involving an interrupt to the system.
WALL ADAPTER Q2 Q4
Q1 BATTERY G2 V1 V2 M1 M2 PB G1
Q3
TO SYSTEM
VS
LTC2952
EN
Q2
Figure 5. Power Path Configuration C
BATTERY Q1 Q3 DC/DC G2 V1 V2 R9 M1 M2 PB R10 S1
2952 F04
TO SYSTEM SHDN
G1
VS
Configuration D: Battery Backup with Push-Button Power Path Controller In this configuration shown in Figure 6, the M1 pin is left floating allowing its own 3A internal pull-up to pull itself above threshold. With M1 high, the device operates such that rising and falling edges on the M2 pin are interpreted as digital on and off commands respectively. In Figure 6, the M2 pin monitors the Wall Adapter Voltage. When power is first applied to the Wall Adapter so
2952f
LTC2952
EN
WALL CAN BE LESS THAN BATTERY
Figure 4. Power Path Configuration B
16
LTC2952 APPLICATIONS INFORMATION
WALL ADAPTER Q2 BATTERY Q1 DC/DC G2 V1 V2 R9 M1 M2 C2 R10 S1
2952 F06
out of the V1 pin when a battery is connected in reverse and protect the part.
TO SYSTEM G1 VS SHDN
LTC2952
EN
PB
Figure 6. Power Path Configuration D
Note however, this reverse battery protection resistor should not be too large in value since the V1 and V2 pins are also used as the anode sense pins of the ideal diode drivers. When the ideal diode driver is on, the VS pin supplies most of the quiescent current of the part (60A typ) and the supply pin supplies the remaining quiescent current (20A typ). Therefore, the recommended 1k reverse battery protection resistor amounts to an additional 20mV (1k * 20A) drop across the P-channel MOSFET. In Figure 7, when the battery voltage is larger than the Wall Adapter voltage, the battery supplies the load current to the DC/DC converter. The ideal diode driver regulates G1 to maintain a fixed voltage drop from V1 to VS of 20mV (typ). Since there is a 20mV drop across the reverse battery protection resistor (R1) then the regulated voltage drop from the battery to the VS pin is 40mV (typ).
WALL ADAPTER Q2 BATTERY R12 1k Q1 G2 * V1 G1 VS EN
that the voltage at the M2 pin rises above its rising trip threshold (0.515V), both of the ideal diode drivers and the DC/DC converter are enabled. Thus power is delivered to the system. As soon as the Wall Adapter voltage falls below its trip threshold, a shutdown sequence is immediately started. At the end of the shutdown sequence, the ideal diode drivers and the DC/DC converter are disabled. Thus power is cut off from the load and the system is in shutdown. Note that once power is delivered to the system, the PB pin can be used to turn off the power. If PB is used to turn off the power in this configuration, there are two methods to turn the power back on: a valid push-button on event at the PB pin or a recycling of the Wall Adapter voltage (bringing the voltage level at the M2 pin down below and then back up above its threshold - a digital on command). Also note that in this application, the voltage threshold of the Wall Adapter input (being monitored at the M2 pin) is usually set higher than the battery input voltage. Therefore, the only time when power is drawn from the battery (V1 pin) to the load is during the shutdown sequence when the voltage at the Wall adapter input (V2 pin) has collapsed below the battery input voltage level. Reverse Battery Protection To protect the LTC2952 from a reverse battery connection, place a 1k resistor in series with the respective supply pin intended for battery connection (V1 and/or V2) and remove any capacitance on the protected pin. Figure 7 shows a configuration with a reverse battery protection on the V1 pin. This resistor will limit the amount of current that flows
DC/DC SHDN
V2 M1 M2 PB S1
2952 F07
LTC2952
*MINIMIZE CAPACITANCE ON V1
Figure 7. Reverse Battery Protection on V1
Push-Button Input and Circuitry The PB pin is a high impedance input to an accurate comparator with a 10A pull-up to an LDO regulated internal supply of 4V. The PB input comparator has a 0.775V falling trip threshold with 25mV hysteresis. Protection circuitry allows the PB pin to operate over wide range from -6V to 28V with an ESD HBM rating of 8kV. The push-button circuitry debounces the input into the PB pin that sets an internal ON/OFF signal. This signal initiates a turn ON/OFF power sequence.
2952f
17
LTC2952 APPLICATIONS INFORMATION
VALID PB `TURN-ON' EVENT INVALID PB `TURN-OFF' EVENT INVALID PB PUSH EVENT INVALID PB RELEASE EVENT INVALID PB PUSH EVENT PB
ONT CAP
OFFT CAP INTERNAL ON/OFF SIGNAL
INT
tDB,ON 26ms
tONT
tDB 26ms
tDB,OFF 26ms
tOFFT
tDB 26ms
tDB,ON 26ms
tONT
tDB,OFF tDB,OFF 26ms 26ms tOFFT
2952 F08
Figure 8. Push-Button Debounce Timing Diagram
The timing diagram in Figure 8 shows the PB pin being debounced and setting an internal ON/OFF signal. Note that a high at the internal ON/OFF signal indicates that the last event was a turn-on command and a low at the internal ON/OFF signal indicates that the last event was a turn-off command. Here specifically the turn-on commmand is a result of a push-button on event and the turn-off command is a result of a push-button off event. Note that a complete push-button consists of a push event and a release event. The push event (falling edge) on and off debounce durations on the PB pin can be increased beyond the fixed internal 26ms by placing a capacitor on the ONT and OFFT pins respectively. The following equations describe the additional debounce time that a push event at the PB pin must satisfy before it is recognized as a valid push-button on or off. tONT = CONT * (9.3M) tOFFT = COFFT * (9.3M) CONT and COFFT are the ONT and OFFT external programming capacitors respectively. Note that during the push event of the push-button off, the INT pin is asserted low after the initial 26ms debounce duration. The INT pin asserts low when the PB pin is held low during the OFFT debounce duration and during the shutdown sequence. If the PB pin pulls high before the OFFT time ends, the INT pin immediately turns high impedance. On the other hand, if the PB pin is still held low at the end of the OFFT time, the INT pin continues to assert low throughout the ensuing shutdown sequence.
On a release event (rising edge) of the push-button switch following a valid push event, the PB pin must be continuously held above its rising threshold (0.8V) for a fixed 26ms internal debounce time. In a typical application, the PB pin is connected to a push-button switch. If the switch exhibits high leakage current (>10A), connecting an external pull-up resistor to V1, V2 and/or VS (depending on the application) is recommended. Furthermore, if the push-button switch is physically located far from the LTC2952's PB pin, signals may couple onto the high impedance PB input. Placing a 0.1F capacitor from the PB pin to ground reduces the impact of signal coupling. Additionally, parasitic series inductance may cause undesirable ringing at the PB pin. This can be minimized by placing a 5k resistor in series and located next to the switch. Accurate Comparator Input Pins VM, PFI, KILL, M1 and M2 VM, PFI, KILL, M1 and M2 are high impedance input pins to accurate comparators with a falling threshold of 0.500V.
VTRIP R1 1% PIN R2 1%
+ - + -
0.5V
2952 F09
Figure 9. Setting the Comparator Trip Point
2952f
18
LTC2952 APPLICATIONS INFORMATION
Note the following differences between some of these pins: the VM pin comparator has no hysteresis while the other comparators have 15mV hysteresis and the M1 pin has a 3A pull-up current while the other input pins do not. Figure 9 shows the configuration of a typical application when VM, PFI, KILL or M2 pin connects to a tap point on an external resistive divider between a positive voltage and ground. Calculate the falling trip voltage from the resistor divider value using: R1 VFALLING- TRIP = 0.5V 1+ R2 Table 1 shows suggested 1% resistor values for various applications.
Table 1. Suggested 1% Resistor Values for the Accurate Comparators (-6.5% nominal threshold)
VSUPPLY (V) 12 10 8 7.5 6 5 3.3 3 2.5 1.8 1.5 1.2 1.0 0.9 0.8 0.7 0.6 VTRIP (V) 11.25 9.4 7.5 7 5.6 4.725 3.055 2.82 2.325 1.685 1.410 1.120 0.933 0.840 0.750 0.655 0.561 R1 (k) 2150 1780 1400 1300 1020 845 511 464 365 237 182 124 86.6 68.1 49.9 30.9 12.1 R2 (k) 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100 100
high impedance input pins. For example, connect the M2 pin to the M1 pin to pull both up above their rising thresholds as shown in Figure 5. The Voltage Monitor and Watchdog Function The first voltage monitor input is PFI. As mentioned before, this pin is a high impedance input to an accurate comparator with 15mV hysteresis. When the voltage at PFI is higher than its rising threshold (0.515V), the PFO pin is high impedance. Conversely, when the voltage level at PFI is lower than its falling threshold (0.500V), the PFO pin strongly pulls down to GND. The second voltage monitor input is VM. The VM pin together with the WDE pin (acting as a watchdog monitor pin) affects the state of the RST output pin. The VM pin is also a high impedance input to an accurate comparator. However, the VM comparator has no hysteresis and hence the same rising and falling threshold (0.500V). When the voltage level at VM is less than 0.5V, the RST pin strongly pulls down to GND. When the voltage level at VM first rises above 0.5V, the RST output pin is held low for another 200ms (tRST) before turning high impedance. After the RST pin becomes high impedance, if the WDE input pin is not left in a high-Z state, the watchdog timer is started. The watchdog timer is reset every time there is an edge (high to low or low to high transition) on the WDE pin. The watchdog timer can expire due to any of the following conditions: 1. No valid edge on the WDE pin in a tWDE (1.6s) time period after the RST pin transitions from pulling low to high impedance. 2. No valid edge on the WDE pin in a tWDE (1.6s) time period since the last valid edge on the WDE pin while the RST pin is high impedance. As shown in the timing diagrams section, when the watchdog timer is allowed to expire while voltage at the VM pin is higher than 0.5V, the RST pin strongly pulls down to ground for tRST (200ms) before again becoming high impedance for tWDE (1.6s). This will continue unless there is an edge at the WDE pin, the voltage at VM goes below 0.5V, or the watchdog function is disabled (by leaving the WDE in a High-Z state).
2952f
In a typical application the M1 pin is usually either connected to ground or left floating. When left floating, the internal 3A pull-up drives the M1 pin high above its rising threshold (0.515V). Note that this 3A pull-up current can be used to pull up any or all of the other
19
LTC2952 APPLICATIONS INFORMATION
INTERNAL ON/OFF SIGNAL DON'T CARE KILL
low-to-high transition) at the WDE pin is detected within the 500ms period to extend the wait period for another 500ms. This KILL Off Wait time (500ms/cycle) is designed to allow the system to finish performing its housekeeping tasks before shutdown. Once the P finishes performing its power-down operations, it can either let the 500ms KILL Off Wait time expire on its own or set the KILL pin low (t5) immediately terminating the KILL Off Wait time. When the KILL Off Wait time expires, the LTC2952 sets EN low, turning off the DC/DC converter connected to the EN pin. When the DC/DC converter is turned off (EN goes low), it can take a significant amount of time for its output level to decay to ground. In order to guarantee that the P has always powered down properly before it is re-started, another 500ms (Enable Lock Out time, tEN, LOCKOUT) timer is started to allow for the DC/DC converter output power level to power down completely to ground. During this Enable Lock Out time, the EN pin remains in its low state. At the end of the 500ms Enable Lock Out time (t6), the LTC2952 goes into its reset state with the EN pin remains strongly pulling down. Aborted Power-On Sequence The power-on sequence is aborted when the P fails to set KILL pin high before the 500ms KILL On Blanking time expires as shown in the timing diagram in Figure 11. When the KILL On Blanking timer expires (t7), the KILL pin is still low indicating that the P/system has failed to power on successfully. When the system failed to set KILL pin high within the specified 500ms time window, the LTC2952 pulls the EN pin low (thus turning off the DC/DC converter) and as a side effect resets the internal ON/OFF signal.
INTERNAL ON/OFF SIGNAL DON'T CARE
EN t1 t2 t3 t 4 t5 t6
2952 F10
tKILL, ON BLANKING Figure 10. Power-On and Power-Off Sequence with KILL Deasserting EN During KILL Off Wait Time
In certain power path configurations where both of the ideal diode drivers are disabled, the watchdog function of the WDE pin is also disabled. Examples of such configurations are configuration C (Figure 5) and configuration D (Figure 6) when both of the ideal diode can be turned off due to a valid push button off or a digital off command. Power-On/Power-Off Sequence Figure 10 shows a normal power-on and power-off timing diagram. Note that in this timing diagram only the clean internal ON/OFF signal is shown. A transition at this internal ON/OFF signal can be caused by a valid debounced push-button ON/OFF or a digital ON/OFF through the mode input pins (M1/M2). In this timing sequence, the KILL pin has been set low since power is first applied to the LTC2952. As soon as the internal ON/OFF signal transitions high (t1), the EN pin goes high impedance and an internal 500ms (tKILL, ON BLANK) timer starts. During this 500ms KILL On Blanking period, the input to KILL pin is ignored and the EN pin remains in its high impedance state. This KILL On Blanking period is designed to give the system sufficient time to power up properly. Once the P/system powers on, it sets the KILL pin high (t 2) indicating that proper power-up sequence is completed. Failure to set KILL pin high at the end of the 500ms KILL on blanking time (t3) will result in immediate system shut down (see Aborted Power-On Sequence segment). After the KILL On Blanking time expires, the system is now in normal operation with power turned on. When the internal ON/OFF signal transitions low (t4), a shut down sequence is immediately started. From the start of the shutdown sequence the system power will turn off in 500ms (tKILL, OFF WAIT), unless an edge (a high-to-low or
KILL
EN t7 tKILL, ON BLANKING tEN, LOCKOUT
2952 F11
Figure 11. Aborted Power-On Sequence
2952f
20
LTC2952 APPLICATIONS INFORMATION
INTERNAL ON/OFF SIGNAL DON'T CARE KILL
EN t8 tKILL, ON BLANKING t9
2952 F12
wait time expires, the WDE pin transitions again (this time from high to low) at t12, causing the 500ms timer to reset again. Finally, the third 500ms timer which starts at t12 expires without any further extension at t13 causing the EN pin to go low, shutting down the DC/DC converter. Setting Up Different Configurations The various configurations discussed previously are summarized here in Table 2, including the ideal diode power paths state (ID1-primary, ID2-secondary). Note that an input above 0.515V (typical rising threshold) on the M1 and M2 pins is indicated with a 1 and an input below 0.500V (typical falling threshold) is represented by a 0. Also, an enabled ideal diode driver is indicated with a 1 and a disabled driver is indicated with a 0.
Table 2. Mode Table
Mode Description 0 1 2 3 4 5 6 7 Both Diodes Enabled Both Diodes Enabled Primary Diode Off, Secondary Diode On Primary Diode Off, Secondary Diode On Power Path Off, PB Overwrite Transitional Power Path Off, PB Overwrite Push-Button Power Path Off Push-Button Power Path On M1 0 0 0 0 1 1 1 1 M2 0 0 1 1 0 0 1 1 EN 0 1 0 1 0 1 0 1 ID1 1 1 0 0 0 1 0 1 ID2 1 1 1 1 0 1 0 1
Figure 12. KILL Initiated Shutdown
KILL Power Turn-Off During Normal Operation Once the system has powered on and is operating normally, the system can turn off power by setting KILL low as shown in the timing diagram in Figure 12. At t9, KILL is set low and this immediately causes the LTC2952 to pull EN low, turning off the DC/DC converter. Extended Power During Turn-Off In the shutdown process, the availability of power can be extended by providing edges to the WDE pin during the KILL Off Wait time. The timing diagram in Figure 13 is similar to the power-on/power-off sequence timing diagram (Figure 10) except for the edges on the WDE pin during the shutdown process. At time t10, the internal ON/OFF signal transitions low. When this happens, the DC/DC converter providing power to the system will be shut off in 500ms unless the WDE pin is toggled. When the WDE pin transitions at t11, the LTC2952 resets the 500ms KILL Off Wait timer. Before this second 500ms
INTERNAL ON/OFF SIGNAL DON'T CARE
EXTENDED HOUSE KEEPING TIME
KILL
DON'T CARE
EN
WDE t10 t11 t12 t13 tEN, LOCKOUT
2952 F13
tKILL, OFF WAIT tKILL, ON BLANKING < tKILL, OFF WAIT < tKILL, OFF WAIT
Figure 13. Power-On/Power-Off Sequence with Extended Shutdown/Housekeeping Wait Time
2952f
21
LTC2952 APPLICATIONS INFORMATION
MODE 0 M1 = 0 M2 = 0 EN = 0 G1 = ON G2 = ON
VALID PB
VALID PB
MODE 1 M1 = 0 M2 = 0 EN = 1 G1 = ON G2 = ON M1 M1
M1
M1
M2
M2
M2
M2 DIGITAL OFF COMMAND
PB CONTROL OF EN PIN
MODE 2 M1 = 0 M2 = 1 EN = 0 G1 = OFF G2 = ON
VALID PB
VALID PB
MODE 3 M1 = 0 M2 = 1 EN = 1 G1 = OFF G2 = ON
MODE 4 M1 = 1 M2 = 0 EN = 0 G1 = OFF G2 = OFF (PB IGNORE) M2 DIGITAL ON COMMAND
MODE 5 M1 = 1 M2 = 0 EN = 1 G1 = OFF G2 = OFF (PB IGNORE) M2 DIGITAL OFF COMMAND M2 DIGITAL ON COMMAND
M1
M1 M2 AND PB CONTROL OF EN PIN AND IDEAL DIODES FUNCTION
M1
M1
M2
MODE 6 M1 = 1 M2 = 1 EN = 0 G1 = OFF G2 = OFF
VALID PB
VALID PB
MODE 7 M1 = 1 M2 = 1 EN = 1 G1 = ON G2 = ON
2952 F14
Figure 14. Mode Transition Diagram
In addition to the mode table, the mode transition diagram in Figure 14 shows all possible interactions between the events on the pins (PB, M1 and M2) and the different modes of the LTC2952 power path behavior. Using Table 2 and Figure 14, it is possible to configure the LTC2952 in many different ways beyond the four discussed in the Operation and Applications Information sections. In modes 0 and 1, both of the ideal diode drivers are enabled all the time. A valid push-button toggles the mode between 0 and 1 (changing the state of the EN pin) without ever turning off of the ideal diodes. These modes are used in Configuration A and B (Figures 3 and 4). In modes 2 and 3, only V2 provides power to the load connected at VS because the primary ideal diode driver is disabled and only the secondary ideal diode driver
is enabled. These modes are used in Configuration B (Figure 4). In modes 4 and 5 both of the ideal diodes are disabled and the input to the PB pin is ignored. Note that mode 5 is a transitional mode. If there is no change at the M1 and M2 pin while in mode 5, the mode eventually transitions into mode 4 after a proper shutdown sequence. A rising edge at M1 in mode 1 or a falling edge at M2 in mode 7 is recognized as a digital off command, which causes a transition to mode 5. When a digital off command is received, the EN pin is driven low and the ideal diodes are disabled after a proper shutdown sequence involving the interrupt alert to the P (INT pin driven low) - refer to the earlier sections for details on the shutdown sequence.
2952f
22
LTC2952 APPLICATIONS INFORMATION
Note that since the PB input is ignored in both mode 4 and 5, the only way to turn on the power path from these two modes is a transition from 0 to 1 at the M2 pin. A transition from 0 to 1 at the M2 pin in modes 4 or 5 is interpreted as a digital on command. This digital on command causes the mode to transition from mode 4 or 5 to mode 7. In mode 7, both of the ideal diodes are enabled and the EN pin goes high impedance. Modes 4, 5 and 7 are used in Configuration D (Figure 6). Notice that in mode 7, both the M2 pin and the PB pin have direct control over the EN pin. A transition from 1 to 0 at the M2 pin in mode 7 is recognized as a digital off command. This digital off command causes a transition to mode 4 after a proper shutdown sequence. On the other hand, a valid push-button off mode 7 transitions the part to mode 6 after a proper shutdown sequence. In both mode 4 and mode 6 the EN pin is driven low. Modes 6 and 7 are used in Configuration C (Figure 5). In mode 4 the ideal diode driver circuitry is disabled, the EN pin is driven low, and the PB input is ignored. On the other hand in mode 6, although both of the primary and secondary ideal diodes are disabled and the EN pin is set low, the PB input is not ignored. A valid push-button transitions the part from mode 6 to mode 7 turning on both the ideal diodes and setting the EN pin high impedance (turning on the DC/DC converter).
TYPICAL APPLICATIONS
Wall Adapter and Battery Automatic Load Switchover with Simple On/Off Push-Button Control and Voltage Monitors for System Power Without P
WALL ADAPTER 5V TO 20V Q2 Si7913DN Q1 Si7913DN VIN VOUT R6 1k R5 1k R8 10k BAT LOW INDICATOR
2952 TA02
2.5V LT1767-2.5 SHDN R7 1k BAT OFF INDICATOR D3
G1 G2 V1 V2 LTC2952 M1 M2
VS PFI EN VM INT KILL RST G1STAT
R4 100k R2 100k
D1
PB
PFO WDE
S1 CONT* 22nF
ONT
GND
OFFT COFFT* 68nF
*OPTIONAL
POWER LOW INDICATOR D2
4.2V SINGLE CELL Li-Ion BATTERY
R3 511k
R1 365k
2952f
23
LTC2952 TYPICAL APPLICATIONS
Wall Adapter and Battery Automatic Load Switchover with Push-Button Control, Voltage Monitors and Watchdog
WALL ADAPTER 12V TO 25V Q2 Si6993DQ Q1 Si6993DQ VIN VOUT R6 10k R1 511k R8 10k R5 10k R2 100k R7 10k LT1767-3.3 SHDN R3 1.3M G1 G2 V1 V2 LTC2952 M1 M2 VS PFI EN VM RST INT G1STAT PFO PB KILL WDE S1 CONT* 22nF ONT GND OFFT COFFT* 68nF P R4 100k 3.3V
9V BATTERY
*OPTIONAL
2952 TA03
Uninterruptible Power Supply with Preferential Wall Adapter Operation and Automatic Load Switchover to Battery with Push-Button Control, Voltage Monitors and Watchdog
WALL ADAPTER 5V TO 30V VIN Q2 Si7421DN Si7941DP CVS 0.1F VOUT LTC1625 RUN/SS Q1 Q3 R3 1.78M VS PFI EN VM LTC2952 M1 RST INT G1STAT M2 PB R10 100k S1 CONT* 22nF ONT GND PFO KILL WDE OFFT COFFT* 68nF P R2 100k R4 100k R5 10k R1 511k R8 10k R7 10k R6 10k 3.3V
5V TO 30V BATTERY
G1 G2 V1 V2
R9 845k
*OPTIONAL
2952 TA04
2952f
24
LTC2952 TYPICAL APPLICATIONS
Direct Power Path Control with Push-Button Control, Voltage Monitors and Watchdog
Si7925DN WALL ADAPTER 5V Q2 Q4 Si7925DN CVS 0.1F POWER ON/OFF INDICATOR R11 1k R1 511k R8 10k R5 10k R2 100k R7 10k
R6 10k
4.2V SINGLE CELL Li-Ion BATTERY
Q1 G1 G2 V1 V2
Q3 VS
D4 EN VM LTC2952 RST INT G1STAT PFO KILL WDE
R3 845k
M1 M2 PFI PB
P
R4 100k S1 CONT* 22nF ONT GND
OFFT COFFT* 68nF
*OPTIONAL
2952 TA05
Critical System with Primary Supply and Temporary Battery Backup with Push-Button Control, Voltage Monitors and Watchdog
PRIMARY POWER 12V TO 30V Q2 SUB75P03-07 Q1 SUB75P03-07 VIN VOUT LTC3728 RUN/SS R3 1.82M G1 G2 V1 V2 R9 2.15M M1 M2 R10 100k C2 0.1nF LTC2952 VS PFI EN VM RST INT G1STAT PFO PB KILL WDE S1 CONT* 22nF ONT GND OFFT COFFT* 68nF P R2 100k R4 100k R5 10k R1 511k R8 10k R7 10k R6 10k 3.3V
12V BATTERY
*OPTIONAL
2952 TA06
2952f
25
LTC2952 PACKAGE DESCRIPTION
F Package 20-Lead Plastic TSSOP (4.4mm)
(Reference LTC DWG # 05-08-1650)
6.40 - 6.60* (.252 - .260) 1.05 0.10 20 19 18 17 16 15 14 13 12 11
6.60 0.10
4.50 0.10
6.40 (.252) BSC
0.45 0.05
0.65 BSC 1 2 3 4 5 6 7 8 9 10 1.10 (.0433) MAX
0 - 8
RECOMMENDED SOLDER PAD LAYOUT 4.30 - 4.50** (.169 - .177)
0.25 REF
0.09 - 0.20 (.0035 - .0079)
0.50 - 0.75 (.020 - .030)
0.65 (.0256) BSC
NOTE: 1. CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS 2. DIMENSIONS ARE IN (INCHES) 3. DRAWING NOT TO SCALE *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED .152mm (.006") PER SIDE **DIMENSIONS DO NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED .254mm (.010") PER SIDE
0.19 - 0.30 (.0075 - .0118) TYP
0.05 - 0.15 (.002 - .006)
F20 TSSOP 0204
2952f
26
LTC2952 PACKAGE DESCRIPTION
UF Package 20-Lead Plastic QFN (4mm x 4mm)
(Reference LTC DWG # 05-08-1710)
0.70 0.05 4.50 0.05 3.10 0.05 2.45 0.05 (4 SIDES)
PACKAGE OUTLINE 0.25 0.05 0.50 BSC RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS BOTTOM VIEW--EXPOSED PAD 4.00 0.10 (4 SIDES) PIN 1 TOP MARK (NOTE 6) 2.45 0.10 (4-SIDES) 0.75 0.05 R = 0.115 TYP 19 20 0.38 0.10 1 2 PIN 1 NOTCH R = 0.30 TYP
(UF20) QFN 10-04
0.200 REF 0.00 - 0.05 NOTE: 1. DRAWING IS PROPOSED TO BE MADE A JEDEC PACKAGE OUTLINE MO-220 VARIATION (WGGD-1)--TO BE APPROVED 2. DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS 4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE 5. EXPOSED PAD SHALL BE SOLDER PLATED 6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
0.25 0.05 0.50 BSC
2952f
27
LTC2952 TYPICAL APPLICATION
Wall Adapter and Battery Automatic Load Switchover with Reverse Battery Protection
WALL ADAPTER 12V TO 25V Q2 Si6993DQ Q1 Si6993DQ VIN VOUT R6 10k R1 511k R8 10k R5 10k R2 100k R7 10k LT1767-3.3 SHDN R3 1.3M 1k G1 G2 V1 EN VM V2 M1 M2 LTC2952 RST INT G1STAT PFO PB KILL WDE S1 CONT* 22nF ONT GND OFFT COFFT* 68nF P VS PFI R4 100k
3.3V
9V BATTERY
*OPTIONAL
2952 TA07
RELATED PARTS
PART NUMBER DESCRIPTION LTC1479 LTC1726 LTC2900 LTC2901 LTC2902 LTC2903 LTC2904/ LTC2905 LTC2906/ LTC2907 LTC2908 LTC2950/ LTTC2951 LTC4411 LTC4412HV PowerPath Controller for Dual Battery Systems Micropower Triple Supply Monitor for 2.5V/5V, 3.3V and ADJ Programmable Quad Supply Monitor Programmable Quad Supply Monitor Programmable Quad Supply Monitor Precision Quad Supply Monitor Three-State Programmable Precision Dual Supply Monitor Dual Supply Monitor with One Pin Selectable Threshold and One Adjustable Input Precision Six Supply Monitors Push-Button On/Off Controller SOT-23 Ideal Diode PowerPath Controller in ThinSOT COMMENTS Complete PowerPath Management for Two Batteries; DC Power Source, Charger and Backup Adjustable RESET and Watchdog Time-Outs Adjustable RESET, 10-Lead MSOP and DFN Packages Adjustable RESET and Watchdog Timer, 16-Lead SSOP Package Adjustable RESET and Tolerance, 16-Lead SSOP Package 6-Lead SOT-23 Package Adjustable Tolerance, 8-Lead SOT-23 and DFN Packages 0.5V Adjustable Threshold and Three Supply Tolerances, 8-Lead SOT-23 and DFN Packages 0.5V Adjustable Threshold, RESET, 8-Lead SOT-23 and DFN Packages P Push-Button Controller Interface with Programmable Debounce On and Off Timing, 8-Lead SOT23 and DFN Packages 2.6A Forward Current, 28mV Regulated Forward Voltage Efficient Diode-ORing, Automatic Switching, 3V to 36V
PowerPath is a trademark of Linear Technology Corporation.
2952f
28 Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
LT 0906 * PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
www.linear.com
(c) LINEAR TECHNOLOGY CORPORATION 2006

▲Up To Search▲

Price & Availability of LTC2952IF

	To Download LTC2952IF Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .